1. Field of the Invention
This invention relates to configurable electrical circuits and in particular, to a method means for providing on-chip programming of each of a plurality of logic elements formed on a chip of semiconductor material to configure each logic element to carry out certain desired functions, and to configure interconnects between the logic elements.
2. Prior Art
Gate arrays are well known in the prior art. Typically a gate array is produced by interconnecting a plurality of active devices in a base array in any one of a number of ways to achieve a desired logic function. As gate arrays become more complex, the simulation of the logic to be achieved from a given interconnection of the active devices in the base array becomes more difficult and is typically carried out using a computer program. The layout of the actual interconnections for the active devices in the base array to yield a finished gate array is then derived using a computer aided design program of a type well known in the art. The process of designing such a structure is complex and reasonably expensive requiring the use of logic simulation and verification programs and semiconductor device layout programs. Accordingly, a need exists for an alternative approach which significantly simplifies the obtaining of a given logic function from a base array.